Interconnect structure for stacked device

ABSTRACT

A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

This patent is a divisional application of U.S. application Ser. No. 13/937,055, filed Jul. 8, 2013, now U.S. Pat. No. 10,096,515 which claims the benefit of U.S. Provisional Application No. 61/798,459 filed Mar. 15, 2013, which are hereby incorporated by reference in their respective entireties.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

As semiconductor technologies further advance, stacked IC devices have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked IC device, active circuits such as logic, memory, processor circuits and the like are fabricated on different semiconductor wafers. Two or more semiconductor wafers are then positioned on top of one another to form a stacked IC. For example, two semiconductor wafers may be bonded together through suitable bonding techniques, and thereafter assembled into a single stacked IC device. One advantage of a stacked IC device is that high density can be achieved. Although existing stacked IC devices and methods of fabricating stacked IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. Improvements in this area are desired.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a cross-sectional view of a stacked integrated circuit (IC) device according to various aspects of the present disclosure.

FIG. 2 is a flow chart of an example method for fabricating a stacked IC device according to various aspects of the present disclosure.

FIGS. 3A-3B and 4-7 are cross-sectional views of an example stacked IC device at fabrication stages constructed according to the method of FIG. 2.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG. 1 is a cross-sectional view of a stacked IC device prior to a bonding process according to various aspects of the present disclosure. FIG. 1 has been simplified for the sake of clarity to better illustrate the inventive concepts of the present disclosure. The figure shows a first semiconductor wafer 100 to be stacked on top of a second semiconductor wafer 200. For example, the first semiconductor wafer 100 is an image sensor, such as a backside illuminated image sensor (BIS), a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS), a charge-coupled device (CCD), an active-pixel sensor (APS), or a passive-pixel sensor. An image sensor may be fabricated by complementary metal-oxide semiconductor (CMOS) process techniques known in the art. For example, a p-type photo active region and an n-type photo active region are formed over a substrate of the image sensor wafer to form a PN junction, which functions as a photodiode. The image sensor wafer 100 may include a transistor to generate a signal related to the intensity or brightness of light that impinges on the photo active region. Continuing with the present example, the second semiconductor wafer 200 is an application-specific integrated circuit (ASIC) wafer.

As shown in FIG. 1, the first semiconductor wafer 100 (shown in an upside down position) includes a first substrate 102 and one or more first inter-metal dielectric (IMD) layers 104 formed over the first substrate. In addition, a plurality of first conductive features, such as conductive features 106 and 108, are formed in the IMD layers 104.

The first substrate 102 includes an elementary semiconductor such as silicon or germanium and/or a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride, and indium phosphide. Other exemplary substrate materials include alloy semiconductors, such as silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. The first substrate 102 may also comprise non-semiconductor materials including soda-lime glass, fused silica, fused quartz, calcium fluoride (CaF₂), and/or other suitable materials. In some embodiments, the first substrate 102 has one or more layers defined within it, such as an epitaxial layer. For example, in one such embodiment, the first substrate 102 includes an epitaxial layer overlying a bulk semiconductor. Other layered substrates include semiconductor-on-insulator (SOI) substrates. In one such SOI substrate, the first substrate 102 includes a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX). In various embodiments, the first substrate 102 may take the form of a planar substrate, a fin, a nanowire, and/or other forms known to one of skill in the art.

The first substrate 102 may include one or more doped regions. In the depicted embodiment, the first substrate 102 is doped with a p-type dopant. Suitable p-type dopants include boron, gallium, indium, other suitable p-type dopants, and/or combinations thereof. The first substrate 102 may also include one or more regions doped with an n-type dopant such as phosphorus, arsenic, other suitable n-type dopants, and/or combinations thereof. Doping may be implemented using a process such as ion implantation or diffusion in various steps and techniques.

In various embodiments, the first substrate 102 may take a form of a planar substrate, a fin, a nanowire, and/or other forms known to one of skill in the art.

The first semiconductor wafer 100 may include various passive and active microelectronic components. These components may include a primary component, such as an image sensor element and a peripheral circuit element, such as one or more field effect transistor. Other examples include P-channel field effect transistors (PFETs), N-channel FETs (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), CMOS transistors, FinFETs, high voltage transistors, high frequency transistors, bipolar junction transistors, resistors, capacitors, diodes, fuses, other suitable devices, and/or combinations thereof. In some embodiments, the peripheral circuit element is operable to interface with or control the primary element. Although, in further embodiments, the peripheral circuit element has no functional relationship to the primary element aside from being collocated on the same substrate 102

The first IMD layers 104 may include silicon oxide, silicon nitride, silicon oxynitride, polyimide, or other suitable materials. The first IMD layers 104 can be formed by chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other suitable deposition processes. The first IMD layers 104 may include multiple layers made by different dielectric materials.

The first conductive features 106 and 108 may be made through any suitable formation processes (e.g., lithography with etching, damascene, dual damascene, or the like) and may be formed using suitable conductive materials such as copper, aluminum, aluminum alloys, copper alloys or the like.

Additional features can be incorporated into the first semiconductor wafer 100 and some of the features described above can be replaced or eliminated for other embodiments of the first semiconductor wafer 100.

The second semiconductor wafer 200 can include similar or different elements, as compared to the first semiconductor wafer 100. For example, the second semiconductor wafer 200 includes a second substrate 202, second IMD layers 204 and a plurality of second conductive features 206 and 208.

FIG. 2 is a flowchart of a method 300 for forming a stacked IC device according to aspects of the present disclosure. FIGS. 3A-3B and 4-7 are cross-sectional views of an example stacked IC device 400 undergoing processes according to the method of FIG. 2. It is understood that additional steps can be provided before, during, and after the method, and some of the steps described can be replaced or eliminated for other embodiments of the method.

Referring to FIGS. 2 and 3A, the method 300 begins at step 302 by bonding the first and second semiconductor wafers, 100 and 200, together through suitable bonding techniques such as direct bonding. In one embodiment, a plurality of bonding pads is formed in the first and second semiconductor wafers, 100 and 200, respectively. In this embodiment, the bonding pads located at the second semiconductor wafer 200 are aligned face-to-face with their corresponding bonding pads located at the first semiconductor wafer 100. In accordance with some embodiments, in a direct bonding process, the connection between the first and second semiconductor wafers, 100 and 200, can be implemented through metal-to-metal bonding (e.g., copper-to-copper bonding), dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding), metal-to-dielectric bonding (e.g., copper-to-oxide bonding), or combination thereof. In some embodiments, the first and second semiconductor wafers, 100 and 200, are connected to each other through suitable three-dimensional structure. An adhesion layer may also be used.

Additionally, a thinning process may be performed to thin either or both substrates from the backside. The thinning process may include a mechanical grinding process and/or a chemical thinning process. For example, a substantial amount of substrate material may be first removed from the first substrate 102 during the mechanical grinding process. Afterwards, the chemical thinning process may apply an etching chemical to the back side of the first substrate 102 to further thin the first substrate 102.

Referring also to FIGS. 2 and 3A, the method 300 proceeds to step 304 by removing a portion of the first substrate 102 to form a substrate trench 120. In one embodiment, a bottom anti-reflection coating (B ARC) layer 110 is formed over a backside of the first substrate 102. The BARC layer 110 may include a nitride material, an organic material, an oxide material and the like. The BARC layer 110 may be formed using suitable techniques such as CVD, PVD and/or the like.

The substrate trench 120 may be formed by lithography and etch processes. As an example, a patterned photoresist layer is formed over the first substrate 102 by processes of spin-on coating, exposure and developing. Then first substrate 102 is etched through the patterned photoresist. The etching process may include dry etching process, wet etching process, and/or combination thereof. The etching process may also include a selective wet etch or a selective dry etch. Example wet etching solutions include a tetramethylammonium hydroxide (TMAH), a HF/HNO3/CH3COOH solution, or other suitable solution. An example dry etching processes may include a biased plasma etching process that uses a chlorine-based chemistry. Other example dry etchant gasses include CF4, NF3, SF6, and He. In some embodiment, a selective etch is performed with adequate etch selectivity with respect to the first IMD layer 104.

In one embodiment, a size of the substrate trench 120 is formed such that it will include more than one deep-interconnection-plug, as shown in FIG. 3A. This will be described in detail below. In another embodiment, a size of the substrate trench 120 is formed such that it includes single future deep-interconnection-plug, as shown in FIG. 3B. The following disclosure will be directed to the embodiment of FIG. 3A, for the sake of example. It is understood that similar steps can be implemented on the embodiment of FIG. 3B.

Referring to FIGS. 2 and 4, the method 300 proceeds to step 306 by filling in the substrate trench 120 with a dielectric layer 130 to form a dielectric block 135 in the first substrate 102. The dielectric layer 130 may include dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, TEOS oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, Parylene, polyimide, low-k dielectric materials, other suitable material, and/or combinations thereof. Common methods for depositing the dielectric layer 130 include thermal oxidation, CVD, high-density plasma CVD (HDP-CVD), PVD, ALD, spin-on deposition, and/or other suitable deposition processes.

In the present embodiment, a process, such as a chemical mechanical polishing (CMP), is applied to planarize the top surface of the dielectric block 135 with the first substrate 102, to achieve a substantial planar surface for a later lithography process.

Referring to FIGS. 2 and 5, the method 300 proceeds to step 308 by forming a patterned mask 140 having deep-interconnect-trench (DIT) openings 145 over the first substrate 102, including the dielectric block 135. The patterned mask 140 may be a photoresist layer or a hardmask. The patterned mask 140 is formed on the top surface of the first substrate 102 and the dielectric block 135 by suitable deposition, photolithography and etching techniques. In the present embodiment, the patterned mask 140 is formed on a substantially flat surface made by the first substrate 102 and the dielectric block 135, which may improve the process window of lithography process. The DIT openings 145 align with the corresponding conductive features, 206 and 208, located in the second semiconductor wafer 200.

Referring to FIGS. 2 and 6, the method 300 proceeds to step 310 by forming deep-interconnection-trenches (DITs) 150 traveling from the first semiconductor wafer 100 to the second semiconductor wafer 200. The DITs 150 are formed with upper portions, 156 and 158, and lower portions, 256 and 258, respectively. Through the DIT openings 145, the upper portions (156 and 158) of the DITs 150 are formed by etching the dielectric block 135 and the first IMD layers 104 and the lower portion of the DITs 150 (256 and 258) are formed by etching the first and second IMD layers, 104 and 204, as well as a bonding interface to two stacked wafers. At least a portion of conductive features 106, 108, 206 and 208 are exposed in the DITs 150.

A suitable etching process includes a dry etch, an anisotropic wet etch, or any other suitable etch. In the present embodiment, a selective etching process with adequate etch selectivity with respect to the conductive features 106 and 108 is applied. As such, the conductive features 106 and 108 may function as a hard mask layer (a “built-in” hard mask) for the etching process of the IMD layers 104 and 204. In one embodiment, a selective etching process may be employed to etch the IMD layers 104 and 204 rapidly while etching only a small portion of the conductive features 106 and 108. An exposed portion of the hard mask layers (e.g., conductive features 106 and 108) are partially etched away, thereby a recess such as recesses 157 and 159 are formed. A depth of the recesses 157 and 159 may vary depending on different applications and design needs.

Referring to FIGS. 2 and 7, the method 300 proceeds to step 312 by filling in the DITs 150 with conductive materials to form deep-interconnect-plugs (DIPs) 160. The DIPs 160 include highly-conductive and low-resistive metal, elemental metal, transition metal, or the like. For example, the DIPs 160 include copper, copper alloy, such as copper magnesium (CuMn), copper aluminum (CuAl) or copper silicon (CuSi), although other materials, such as tungsten, aluminum could alternatively be utilized. The DIPs 160 may be formed by any suitable method known in the art such as PVD, sputter, CVD, electroplating and/or the like. In one embodiment, the DIP 160 s are further surrounded by a barrier layer to prevent diffusion and/or provide material adhesion. The barrier layer may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN) or tantalum silicon nitride (TaSiN). The DIPs 160 are formed with an upper portion having the first width w₁ and a lower portion having the second width w₂. In the present embodiment, the first width w₁ is substantially larger than the second width w₂. The dielectric block 135 and the first IMD layers 104 provide electric isolation to the upper portion of the DIP 160, while the first and second IMD layers, 104 and 204, provide electric isolation to the lower portion of the DIP 160. Additionally, a chemical mechanical polishing (CMP) may be applied to remove the conductive material for planarization effect if a desired topography is needed.

It should be noted that while FIG. 7 illustrates two semiconductor wafers stacked together, one skilled in the art will recognize that the stacked semiconductor device shown in FIG. 7 is merely an example. There may be many alternatives, variations and modifications. For example, the stacked semiconductor device may accommodate more than two wafers.

Based on the above, the present disclosure offers a stacked IC device employing structures and formations of a dielectric block and a deep-interconnection-trench. The dielectric block provides a substantially planner surface for lithography process of the deep-interconnection-trench and it has demonstrated process window improvement. The deep-interconnection-trench is formed by a selective etching process with adequate etch selectivity to utilize a “built-in” hard mask to gain process flexibility and control.

The present disclosure provides many different embodiments of a stacked integrated circuit (IC) device. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers. The conductive deep-interconnection-plug includes an upper portion formed over a first side of a hard mask layer. The upper portion is of a first width. The conductive deep-interconnection-plug also has a lower portion formed over a second side of the hard mask layer. The lower portion is of a second width, which is substantially less than the first width.

In another embodiment, a stacked integrated circuit (IC) device includes a first semiconductor element having a first substrate and a dielectric block disposed in the first substrate, and first conductive features. The stacked IC device also has a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and second conductive features over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first and second conductive features. The conductive deep-interconnection-plug includes an upper portion is isolated by the dielectric block and a lower portion with a width, which is much small than a width of the upper portion.

In yet another embodiment, a method for fabricating a stacked integrated circuit (IC) device includes providing a first semiconductor element. The first semiconductor element includes a first substrate, a first inter-metal-dielectric (IMD) layer over the first substrate and a conductive feature in the first IMD layer. The method also includes bonding the first semiconductor element on a second semiconductor element. The second semiconductor element includes a second substrate, a second inter-metal-dielectric (IMD) layer over the second substrate and a second conductive feature in the second IMD layers. The method also includes forming a substrate trench in the first substrate, filling in the substrate trench with a dielectric material to form a dielectric block with a substantial flat surface with the first substrate, forming a patterned mask over the flat fist substrate and the dielectric block, etching the dielectric block, the first IMD layer and the partial second IMD layer through the pattern mask to form a deep-interconnection-trench and filling in the deep-interconnection-trench with conductive materials to form a deep-interconnection-plug to couple the first and second conductive features.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A method, comprising: bonding a first wafer to a second wafer, wherein the first wafer includes a first substrate and a first conductive feature formed within a first inter-metal dielectric (IMD) layer, and wherein the second wafer includes a second substrate and a second conductive feature formed within a second IMD layer; forming, after the bonding, a recess in the first substrate; filling the recess with a dielectric material; forming a patterned mask over the dielectric material; etching a trench that vertically extends through the patterned mask, through the dielectric material, through the first substrate, through the first IMD layer, and that partially extends through the second IMD layer; removing the patterned mask after the trench has been etched; and forming an interconnection plug by filling the trench with a conductive material.
 2. The method of claim 1, wherein the forming the recess is performed such that the recess is at least partially aligned with the first conductive feature and the second conductive feature.
 3. The method of claim 1, wherein the forming the recess comprises forming a plurality of recesses in the first substrate.
 4. The method of claim 1, wherein: the bonding comprises bonding the first IMD layer with the second IMD layer.
 5. The method of claim 4, wherein the forming the recess comprises an etching process having an etching selectivity between the first IMD layer and the first substrate.
 6. The method of claim 1, wherein the filling the recess comprises completely filling the recess with the dielectric material.
 7. The method of claim 1, further comprising: after the filling the recess with the dielectric material, planarizing a surface of the dielectric material using a chemical mechanical polishing (CMP) process, wherein the patterned mask is formed on a planarized surface of the dielectric material.
 8. The method of claim 1, wherein the forming the patterned mask comprises forming a patterned mask having an opening that is at least partially aligned with the first conductive feature and with the second conductive feature.
 9. The method of claim 8, wherein: the etching the trench is performed such that the trench stops at the second conductive feature; and the interconnection plug is formed to electrically couple together the first conductive feature and the second conductive feature.
 10. The method of claim 1, wherein the etching the trench is performed using a single etching process, wherein the single etching process partially etches away the first conductive feature, and wherein the single etching process has an etching selectivity between the first conductive feature and the first IMD layer.
 11. The method of claim 1, wherein the interconnection plug is formed to have a wider upper portion and a narrower lower portion.
 12. A method, comprising: bonding a first wafer with a second wafer, wherein the first wafer includes a first inter-metal dielectric (IMD) layer that includes a first conductive element formed over a first substrate, and wherein the second wafer includes a second IMD layer that includes a second conductive element formed over a second substrate; forming, a dielectric block in the first substrate; forming a patterned mask over the dielectric block, wherein the patterned mask includes an opening that is vertically aligned with at least the first conductive element or with the second conductive element; vertically extending, using a single etching process, the opening through the dielectric block, the first substrate, the first IMD layer, and partially through the second IMD layer, wherein the first conductive element serves as a mask during the single etching process; and filling the opening with a conductive material, thereby forming an interconnection plug that electrically couples together the first conductive element with the second conductive element.
 13. The method of claim 12, wherein the single etching process partially etches the first conductive element.
 14. The method of claim 12, wherein the interconnection plug is formed to have a wider first portion that is located in the first IMD layer and a narrower second portion that is located in both the first IMD layer and the second IMD layer.
 15. A method comprising: providing a first semiconductor element, the first semiconductor element comprising: a first substrate; a first inter-metal-dielectric (IMD) layer over the first substrate; and a first conductive feature in the first IMD layer; bonding the first semiconductor element to a second semiconductor element, wherein the second semiconductor element comprises: a second substrate; a second inter-metal-dielectric (IMD) layer over the second substrate; and a second conductive feature in the second IMD layer; forming a substrate trench in the first substrate; completely filling in the substrate trench with a dielectric material to form a dielectric block; forming a patterned mask over the first substrate and the dielectric block; etching the dielectric block, the first IMD layer and the second IMD layer through the patterned mask to form a deep-interconnection-trench; and filling in the deep-interconnection-trench with conductive materials to form a deep-interconnection-plug that electrically couples the first conductive feature with the second conductive feature.
 16. The method of claim 15, wherein the etching is performed using a single etching process, and wherein the patterned mask serves as an etching mask during an entirety of the single etching process.
 17. The method of claim 15, wherein the etching has an etch selectivity between the first conductive feature and the first IMD layer such that the first IMD layer is etched through vertically while the first conductive feature is partially, but not completely, etched.
 18. The method of claim 17, wherein the first conductive feature serves as an etch hard mask during the etching.
 19. The method of claim 15, wherein the forming the deep-interconnection-plug comprises forming the deep-interconnection-plug having a wider first portion and a narrower second portion.
 20. The method of claim 15, wherein the etching is performed such that the deep-interconnection-trench extends through the first conductive feature but stops at the second conductive feature. 